Semiconductor devices, such as memory cells, often incorporated within computer systems for storing data, may be fabricated in one or more arrays of individual memory cells. Memory cells may be configured to be written to, read from, or both using digit lines (which may also be known in the art as “bit lines” or “sense lines”) and access lines (which may also be known in the art as “word lines”). Digit lines may electrically interconnect memory cells, or conductive elements therein, along columns of an array, while the access lines may electrically interconnect memory cells, or conductive elements therein, along rows of the memory array. Each memory cell of a memory array may be uniquely addressed through a unique combination of a digit line and an access line.
There is a continuing push to decrease the size of memory devices and to simplify the complexity and amount of wiring associated with memory devices so as to increase the density at which such memory devices may be fabricated. Often, working to achieve these goals increases the risk of defects or errors resulting from imprecisions in the device fabrication processes. For example, attempts to increase the density of memory arrays have included orienting the memory cells of the memory arrays vertically, such that source/drain regions of transistors within the memory cells are vertically aligned with one another. In such vertical transistors, digit lines, which may comprise doped regions of semiconductor material, are “buried,” i.e., are disposed vertically lower within the semiconductor material than upper regions of the vertical transistor. While the vertical orientation may decrease the footprint of the vertical transistor, providing doping to a buried region of the semiconductor material may present challenges.
Conventional methods of doping the semiconductor material to form buried, doped elements of a vertical transistor include implanting a dopant into an exposed surface of the semiconductor material at a floor exposed by a trench. The implanted dopant is then subjected to a thermal treatment to diffuse the dopant to regions of the semiconductor material at which the dopant is desired. This desired dopant destination is often vertically below a region of the semiconductor material that is to remain undoped.
As the dopant diffuses to the desired destination, the dopant may also diffuse into regions of the semiconductor material where doping is not desired; therefore, achieving a desired dopant concentration at the desired destination may include allowing the dopant to diffuse throughout a broad region of the semiconductor material, even though dopant concentrations may not be needed throughout much of the broad region. Accordingly, a greater amount of dopant may need to be implanted than is eventually diffused to and used at the desired destination. Moreover, to avoid the dopant diffusing through too broad a region of the semiconductor material, the ultimate concentration of dopant at the desired destination may be limited. Additionally, with the conventional implant technique, it may be challenging to supply a consistent amount of dopant to exposed material surfaces at the floors of a plurality of trenches. For example, if neighboring trenches have floors of differing widths due to, for example, imprecisions in trench formation processes, the amount of dopant implanted into the exposed material surface at the floor of one trench may differ from the amount of dopant implanted into the exposed material surface at the floor of another trench. Therefore, the conventional implantation and diffusion doping technique may not consistently dope the material across a plurality of trenches.